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We are seeking an experienced FPGA designer to implement a PCIe interface on a Xilinx Artix-7 FPGA. Project Requirements: PCIe Gen2 support x1 or x2 lane configuration The PCIe interface should generate and transfer data PCB-design consideration (if possible, could not be included) Deliverables include tested design, documentation, and support for integration Preferred Skills: Strong background in FPGA design (Xilinx Artix-7) Experience with PCIe protocol implementation Familiarity with Xilinx Vivado tools Engagement: Freelance/contract Please include your availability, estimated timeline, and expected budget or hourly rate in your proposal We look forward to setting up a first call to discuss the project in detail.